1. Field
The present invention relates to a liquid crystal display panel, and more particularly, to a method of fabricating a liquid crystal display panel capable of reducing a fabricating cost and simplifying a fabricating process.
2. Description of the Related Art
In general, a liquid crystal display device represents an image by means of adjusting a transmittance of a liquid crystal material using an electric field. For this purpose, the liquid crystal display device comprises a liquid crystal display panel in which the liquid crystal cells are arranged in a matrix pattern, and a driving circuit for driving the liquid crystal display panel.
The liquid crystal display panel includes a thin film transistor array substrate and a color filter array substrate facing each other, a spacer located for fixedly maintaining a cell gap between two substrates and a liquid crystal stuffed to the cell gap.
The thin film transistor array substrate includes gate lines and data lines, a thin film transistor formed as a switching device at every crossing of the gate lines and the data lines, a pixel electrode formed for every liquid crystal cell and connected to the thin film transistor, and an alignment film applied on them. The gate lines and the data lines receive signal from the driving circuits through each of the pad parts. The thin film transistor, in response to a scan signal supplied to a gate line, supplies to the pixel electrode a pixel voltage signal provided to the data line.
The color filter array substrate includes a color filter formed for every liquid crystal cell, a black matrix for reflecting external light and separating between the color filters, a common electrode commonly supplying a reference voltage to the liquid crystal cells, and the alignment film applied on them.
The liquid crystal display panel is fabricated by combining the thin film transistor array substrate and the color filter array substrate which are separately manufactured, injecting the liquid crystal material between the substrates and sealing the substrates having the liquid crystal material therebetween.
FIG. 1 is a plan view illustrating a part of a related art thin film transistor array substrate, and FIG. 2 is a sectional view illustrating the thin film transistor array substrate taken along line I-I′ in FIG. 1.
The thin film transistor array substrate, shown in FIG. 1 and FIG. 2, includes gate lines 2 and data lines 4 crossing with each other and having a gate insulating film 44 therebetween on a lower substrate 42, a thin film transistor 6 formed at every crossing, and a pixel electrode 18 formed in the cell region arranged by the crossing fashion. Further, the thin film transistor array substrate includes a storage capacitor 20 formed at an overlapped part of the pixel electrode 18 and a pre-stage gate line 2, a gate pad part 26 connected to the gate line 2 and a data pad part 34 connected to the data line 4.
The thin film transistor 6 includes a gate electrode 8 connected to the gate line 2, a source electrode 10 connected to the data line 4, a drain electrode 12 connected to a pixel electrode 18, and an active layer 14 of a semiconductor pattern 68 which defines a channel between the source electrode 10 and the drain electrode 12 and overlaps the gate electrode 8. The active layer 14 overlaps a lower data pad electrode 36, a storage electrode 22, the data line 4, the source electrode 10 and the drain electrode 12, and further includes a channel portion defined between the source electrode 10 and the drain electrode 12. An ohmic contact layer 48 of the semiconductor pattern 68 for making an ohmic contact with the source electrode 10 and the drain electrode 12 are further formed on the active layer 14. The thin film transistor 6 responds to the gate signal supplied to the gate line 2 and makes a pixel voltage signal supplied to the data line 4 be charged to the pixel electrode 18.
The pixel electrode 18 is connected to the drain electrode 12 of the thin film transistor 6 via a first contact hole 16 passing through a passivation film 50. The pixel electrode 18 generates a potential difference along with the common electrode formed on the upper substrate (not shown) by a pixel voltage charged. By this potential difference, the liquid crystal material located between the thin film transistor substrate and the upper substrate rotates due to a dielectric anisotropy, and allows incident light through the pixel electrode 18 from the light source (not shown) to be transmitted to the upper substrate.
The storage capacitor 20 includes a pre-stage gate line 2, a storage electrode 22 overlapping the pre-stage gate line 2 having the gate insulating film 44, the active layer 14 and the ohmic contact layer 48 therebetween, and the pixel electrode 18 connected through a second contact hole 24 formed at the passivation film 50 and overlapped with the storage electrode 22 having the passivation film 50 therebetween. The storage capacitor 20 makes the pixel voltage be charged to the pixel electrode 18 stably maintain until a next pixel voltage is charged.
The gate line 2 is connected to a gate driver (not shown) through the gate pad part 26. The gate pad part 26 includes a lower gate pad electrode 28 extending from the gate line 2 and an upper gate pad electrode 32 connected to the lower gate pad electrode 28 via a third contact hole 30 passing through both of the gate insulating film 44 and the passivation film 50.
The data line 4 is connected to the data driver (not shown) through the data pad part 34. The data pad part 34 includes the lower data pad electrode 36 extending from the data line 4 and an upper data pad electrode 40 connected to the lower data pad electrode 36 via a fourth contact hole 38 passing through the passivation film 50.
FIGS. 3A to 3G are sectional views illustrating a method of fabricating a thin film transistor array substrate of a related art liquid crystal display panel.
First of all, a gate metal layer is formed by a deposition method such as a sputtering method on the lower substrate 42. Thereafter, as shown in FIG. 3A, a printing plate 99 is prepared, wherein the printing plate 99 includes a resist 98 that is printed in a groove 55 of a gate pattern shape representing a gate line, a gate electrode 8, and a lower gate pad electrode 28. Herein, the printing plate 99 may include an organic material such as acrylic or BCB (benzocyclobutene), and may be made by etching a glass substrate itself. A printing roller 88 is contacted with the printing plate 99 while rotating, thereby adhering or transferring the resist 98 to the printing roller 88, as shown in FIG. 3B.
The printing roller 88 having the resist 98 is rotated and contacted with the lower substrate 42 having the gate metal layer, thereby forming a resist pattern 98 of the gate pattern shape on the lower substrate 42. The gate metal layer is etched by using the resist pattern 98 as a mask, to thereby form the gate pattern including the gate line 2, the gate electrode 8, and the lower gate pad electrode 28, as shown in FIG. 3C. Herein, a metal for the gates includes chrome (Cr), molybdenum (Mo), aluminum (Al) and the like in a form of a single-layer structure or a double-layer structure.
A gate insulating film 44 is formed on the lower substrate 42 provided with the gate pattern. The gate insulating film 44 is made of an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx)
An amorphous silicon layer and a n+ amorphous silicon layer are sequentially formed on the lower substrate 42 having the gate insulating film 44 thereon by a deposition technique such as plasma enhanced chemical vapor deposition (PECVD) and sputtering.
A resist pattern is formed on the n+ amorphous silicon layer by using a printing roller and a printing plate, in which a resist is printed in a groove with a shape of a semiconductor pattern shape. Thereafter, the amorphous silicon layer and the n+ amorphous silicon layer are patterned using the resist pattern as a mask. Accordingly, as shown in FIG. 3D, the semiconductor pattern 68 is formed. The semiconductor pattern 68 has a double-layer structure in which the active layer 14 and the ohmic contact layer 48 are stacked.
A source/drain metal layer is entirely formed on the lower substrate 42 provided with the semiconductor pattern 68 by a deposition technique such as plasma enhanced chemical vapor deposition (PECVD) and sputtering.
A resist pattern is formed on the source/drain metal layer by using a printing roller and a printing plate, in which a resist is printed in a groove with a shape of a source/drain pattern having a data line 4, a source electrode 10, a drain electrode 12, a storage electrode 22 and a lower data pad electrode 36. Thereafter, the source/drain metal layer is patterned using the resist pattern as a mask. Accordingly, there is formed the source/drain pattern including the data line 4, the source electrode 10, the drain electrode 12, the storage electrode 22 and the lower data pad electrode 36.
Next, the ohmic contact layer 48 of the channel portion is etched using the source electrode 10 and the drain electrode 12 as a mask, thereby etching the active layer 14 of the channel portion, as shown in FIG. 3E.
Herein, a metal for the source/drain pattern includes molybdenum (Mo), titanium (Ti), tantalum (Ta) or a molybdenum alloy.
A passivation film 50 is entirely formed on the lower substrate 42 having the source/drain pattern thereon by a deposition technique such as plasma enhanced chemical vapor deposition (PECVD). Thereafter, a resist pattern is formed on the lower substrate 42 provided with the passivation film 50 by using a printing roller and a printing plate having a groove with a printed resist. And then, the passivation film 50 is patterned through the use of the resist pattern as a mask, to thereby form first to fourth contact holes 16, 24, 30 and 38 as shown in FIG. 3F. The first contact hole 16 is formed in such a manner to pass through the passivation film 50 and exposes the drain electrode 12, whereas the second contact hole 24 is formed in such a manner to pass through the passivation film 50 and exposes the storage electrode 22. The third contact hole 30 is formed in such a manner to pass through the passivation film 50 and the gate insulating film 44 and exposes the lower gate pad electrode 28, whereas the fourth contact hole 38 is formed in such a manner to pass through the passivation film 50 and exposes the lower data pad electrode 36. Herein, the passivation film 50 is made of an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx).
A transparent electrode material is entirely deposited on the lower substrate 42 provided with the passivation film 50 by a deposition technique such as sputtering and the like. Then, a resist pattern is formed on the lower substrate 42 provided with the passivation film 50 by using a printing roller and a printing plate, in which a resist is printed in a groove with a shape of a transparent electrode pattern having a pixel electrode 18, an upper gate pad electrode and an upper data pad electrode. Thereafter, the transparent electrode material is patterned by using the resist pattern as a mask. Accordingly, the transparent electrode pattern including the pixel electrode 18, the upper gate pad electrode 32, and the upper data pad electrode 40 is formed. The pixel electrode 18 is electrically connected, via the first contact hole 16, to the drain electrode 12 while being electrically connected, via the second contact hole 24, to the storage electrode 22 overlapping a pre-stage gate line 2. The upper gate pad electrode 32 is electrically connected, via the third contact hole 30, to the lower gate pad electrode 28. The upper data pad electrode 40 is electrically connected, via the fourth contact hole 38, to the lower data pad electrode 36. In this connection, the transparent electrode material is made of indium-tin-oxide (ITO), tin-oxide (TO) or indium-zinc-oxide (IZO).
In such a method of manufacturing a related art thin film transistor array substrate, since the patterning process using the printing plate is performed over five times to manufacture thin film transistor array substrate, the manufacturing process is complicated, which is a major factor in increasing the manufacturing cost of the liquid crystal display panel. This is because one patterning process using the printing plate includes a lot of processes such as thin film deposition, cleaning, photolithography, etching, photo-resist stripping, inspection processes and the like. Accordingly, recently, the thin film transistor array substrate has been developed using a reduced number of mask processes. There is a need to simplify the manufacturing process and thus to save the manufacturing cost. Also, since a stripper used in a stripping process is very expensive and becomes wastewater after being used one time, the thin film transistor array substrate reducing the number of stripping processes is beneficial.